PowerPC 440 (Xilinx)
7-stage pipeline
http://www.xilinx.com/products/silicon_solutions/fpgas/virtex/virtex5/capabilities/PowerPC_440.htm
1,100 DMIPS @ 550MHz (2.0 DMIPS/MHz)
PowerPC 405
5-stage
700 DMIPS @ 450MHz (1.55 DMIPS/MHz)
Altera NIOS II (f)
6-stage pipeline,
Stratix III/IV
upto 340 MIPS @290MHz, 1020 ALUTs (1.183 MIPS/MHz)
Cyclone III
upto 195 MIPS @175MHz, 1800 LEs (1.109 MIPS/MHz)
Xilinx Microblaze
5-stages, 1.19 DMIPS/MHz
http://www.xilinx.com/products/design_resources/proc_central/microblaze_per.htm
Virtex-5
280 DMIPS @235 MHz, 1,027 LUTs (no MMU)
Spartan-3
125 DMIPS @105 MHz, 1,809 LUTs
Lattice Mico32
Through the Designware license, designers can port Nios-based designs from an FPGA-platform to a mass production ASIC-device
mercredi 1 octobre 2008
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